The present invention relates to an electronic device and a method of manufacturing the same. Particularly, the invention is concerned with a technique applicable effectively to an electronic device which adopts a flip-chip mounting technique.
As an electronic device there is known an electronic device called MCM (Multi Chip Module). In MCM, plural semiconductor chips each incorporating an integrated circuit are mounted on a wiring board to implement one synthetic function. In connection with MCM, the adoption of a flip-chip mounting technique is becoming more and more popular in which a semiconductor chip (flip-chip) with salient electrodes formed on electrode pads on a circuit-formed surface is mounted onto a wiring board. This is for increasing the data transfer speed and for the reduction of size.
As to the flip-chip mounting technique, various mounting methods have been proposed and put to practical use. For example, mounting methods called CCB (Controlled Collapse Bonding) and ACF (Anisotropic Conductive Film) mounting are adopted practically.
In CCB method, solder bumps of, for example, a ball shape are formed as bump electrodes (salient electrodes) on electrode pads of a semiconductor chip, then the semiconductor chip is put on a wiring board, and thereafter a heat treatment for melting the solder bumps is performed to connect connection parts as wiring portions on the wiring board with the electrode pads of the semiconductor chip electrically and mechanically.
In ACF mounting method, stud bumps of such as gold (Au) are formed as bump electrodes (salient electrodes) on electrode pads of a semiconductor chip, then the semiconductor chip is put on a wiring board through an anisotropic conductive resin (ACF) of a sheet shape as a bonding resin, thereafter the semiconductor chip is compression-bonded to the wiring board under heating and the stud bumps are electrically connected to connection parts on the wiring board. The anisotropic conductive resin comprises an insulating resin and a large number of conductive particles dispersed and mixed therein.
Having studied the foregoing flip-chip mounting techniques, the present inventors found out the following problems.
(1) There are various types of arrays as pad arrays of a semiconductor chip. Among them is included a central pad array in which plural electrode pads are arranged in a line along a central region which extends along a center line in X or Y direction of a circuit-formed surface of a semiconductor chip. This central pad array is adopted, for example, for a semiconductor chip in which is incorporated a DRAM (Dynamic Random Access Memory) as a memory circuit.
For example in the case of a DRAM there are the following requirements with respect to the arrangement of electrode pads (bonding pads). Electrode pads should be arranged near an input/output circuit for the reduction of wiring inductance. Moreover, for the prevention of device damage in bonding process, a semiconductor device should not be formed just under electrode pads. Further, for the purpose of improving the operating speed, the distance from an input/output circuit up to a remotest portion in a memory mat should be made as short as possible. Satisfying these requirements results in such a layout on DRAM chip as shown in FIG. 21, in which electrode pads are arranged centrally in a long side direction of the chip. In FIG. 21, the numeral 30 denotes a DRAM chip, MARY denotes a memory array, PC denotes a peripheral circuit, I/O denotes an input/output circuit, and BP denotes an electrode pad.
In the case of a central pad array, the array of bump electrodes formed respectively on the electrodes pads is also a central bump array. If such a semiconductor chip is used in flip chip mounting, it is impossible to take balance of the chip, so that the chip tilts with respect to one main surface of a wiring board. Thus, in the case of a semiconductor chip having a central pad array, it is difficult to effect flip chip mounting. As another example of a pad array (bump array) with a semiconductor chip not well-balanced, there is, other than the central pad array, a one-side pad array (one-side bump array) in which plural electrodes pads are arranged in a line along one of two opposed sides of the chip.
(2) In ACF mounting method, stud bumps are compression-bonded to connection parts on a wiring board with a thermoshrinking force (a shrinking force developed upon return to a state of normal temperature from a heated state) or a thermocuring shrinking force (a shrinking force developed upon curing of a thermosetting resin) of an anisotropic conductive resin interposed between a wiring board and a semiconductor chip. On the other hand, since the thermal expansion coefficient of an anisotropic conductive resin is generally larger than that of stud bumps, the amount of expansion in the thickness direction of the anisotropic conductive resin is larger than that in the height direction of stud bumps. Consequently, there may occur a poor connection such that stud bumps come off from connection parts on the wiring board due to the influence of heat. Therefore, it is necessary that the volume of the anisotropic conductive resin between the wiring board and the semiconductor chip be made as small as possible.
In this connection, a technique for diminishing the volume of an anisotropic conductive resin between a wiring board and a semiconductor chip is disclosed, for example, in Japanese Published Unexamined Patent Application No. Hei 10(1998)-270496 (U.S. Pat. No. 6,208,525). According to the technique disclosed in this unexamined publication, as shown in FIG. 12 thereof, xe2x80x9ca groove 19A is formed in a rigid wiring board 19, electrode pads 4A formed within the groove 19A, and the electrode pads 4A and bump electrodes 15 are connected together within the groove 19. According to this configuration, a gap between the wiring board 19 and a semiconductor chip 10 becomes narrower by an amount corresponding to the depth of the groove 19A in comparison with the case where there is no top insulating layer on the wiring board and the electrodes pads 4A and a top wiring layer are exposed, whereby it is possible to reduce the thickness of an adhesive (anisotropic conductive resin) 16 interposed between the wiring board 19 and the semiconductor chip 10.xe2x80x9d
However, according to the above configuration wherein a groove is formed in a wiring board and electrode pads (connection parts) on the wiring board and bump electrodes (stud bumps) are connected together within the groove, there arises a new problem.
In the case of electrode pads on a semiconductor chip, a plane size depends on the array pitch of the electrode pads (a pad array pitch) and the narrower the pad array pitch, the smaller the plane size. If a thinner gold wire is used to form stud bumps of a smaller diameter with such a decrease in size of the electrode pads, the height of each stud bump also becomes smaller accordingly. That is, if the pad array pitch differs, the stud bump height differs as well.
On the other hand, in a certain electronic device, such as MCM, several types of semiconductor chips different in the degree of integration and in function are mounted on a single wiring board, but these semiconductor chips are not always equal in pad array pitch. With different pad array pitches, there are different stud bump heights, so in the case of a semiconductor chip wherein the stud bump height is larger than the depth from one main surface of a wiring board to connection parts thereof, it is possible to easily effect connection between the wiring board connection parts and the stud bumps, but in the case of a semiconductor chip wherein the stud bump height is smaller than the depth from one main surface of a wiring board to connection parts thereof, it is difficult to effect connection between the wiring board connection parts and the stud bumps.
If a depth position of the wiring board connection parts is set to match the semiconductor chip having the smallest stud bump height out of the semiconductor chips to be mounted on the wiring board, stud bumps can be connected to the wiring board connection parts even in a semiconductor chip having the smallest stud bump height. In this case, however, in a semiconductor chip having a large stud bump height, the volume of an anisotropic conductive resin interposed between the semiconductor chip and the wiring board becomes large and there may occur a poor connection such that the stud bumps come off from the wiring board connection parts under the influence of heat.
It is an object of the present invention-to provide a technique capable of suppressing a tilt of a semiconductor chip relative to one main surface of a wiring board.
It is another object of the present invention to provide a technique which permits several types of semiconductor chips different in pad array pitch to be mounted on a single wiring board.
The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
A brief description will be given below about typical inventions out of those disclosed herein.
(1) An electronic device according to the present invention includes:
a semiconductor chip having a plurality of electrode pads on one main surface thereof;
a wiring board having a plurality of connection parts exposed on a surface thereof; and
a plurality of salient electrodes arranged in a line between the electrode pads of the semiconductor chip and the connection parts of the wiring board,
the plural connection parts of the wiring board being located at a deeper position than the one main surface of the wiring board in a depth direction from the one main surface.
The wiring board further includes an insulating film comprising the one main surface and an opening formed in the insulating film, and the plural connection parts are disposed in a bottom of the opening.
The insulating film is present straddling a peripheral edge of the semiconductor chip.
A plane size of the opening is smaller than that of the semiconductor chip, while a plane size of the insulating film is larger than that of the semiconductor chip.
According to the above means (1), the height of the salient electrodes is absorbed by the depth from the one main surface of the wiring board to the connection parts at the time of flip-chip mounting of the semiconductor chip, so that it is possible to suppress a tilt of the semiconductor chip relative to the one main surface of the wiring board.
(2) An electronic device according to the present invention includes:
a first semiconductor chip having a plurality of first electrode pads arranged at a first pad array pitch on one main surface thereof;
a second semiconductor chip having a plurality of second electrode pads arranged on one main surface thereof at a second pad array pitch smaller than the first pad array pitch;
a wiring board having in a first area of one main surface thereof a plurality of first connection parts arranged correspondingly to the plural first electrode pads and also having in a second area different from the first area on the one main surface a plurality of second connection parts arranged correspondingly to the plural second electrode pads;
a plurality of first salient electrodes each disposed between each of the first electrode pads and each of the first connection parts and providing an electrical connection between the two; and
a plurality of second salient electrodes each disposed between each of the second electrode pads and each of the second connection parts and providing an electrical connection between the two, the plural first connection parts and the plural second connection parts being disposed at a deeper position than the one main surface of the wiring board in a depth direction from the one main surface, and
the second plural salient electrodes having a multistage bump structure with a larger number of stages than the plural first salient electrodes.
The wiring board further includes an insulating film formed on the one main surface thereof, a first opening in the insulating film in the first area of the one main surface, and a second opening formed in the insulating film in the second area of the main surface, the plural first connection parts are disposed in a bottom of the first opening and the plural second connection parts are disposed in a bottom of the second opening.
The second salient electrodes have a multi-stage bump structure having base bumps connected to the second electrode pads of the second semiconductor chip and stack bumps stacked on the base bumps.
The second salient electrodes have a multi-stage bump structure having base bumps connected to the second electrode pads of the second semiconductor chips, first stack bumps stacked on the base bumps, and second stack bumps stacked on the first stack bumps.
According to the above means (2), at the time of flip-chip mounting the first and second semiconductor chips, salient electrodes can be connected to the second connection parts of the wiring board also in the second semiconductor chip, so that the first and second semiconductor chips different in pad array pitch can be mounted on a single wiring board.